Digital circuits are continually being pressed for higher operating frequencies. In such context, frequency dividers that are implemented with counters consistently suffer from the ripple delays associated with multiple flip-flop stages or latches and logic gates. However, the switching time of the latches limits the clock frequency that can be divided. As the upper limit on clock frequency is limited so is the speed of associated circuits. Logic devices of limited complexity and elevated speed capability are preferred for advanced high-speed digital signal processing applications. These logic circuits require high speed clock divider circuits to preserve the overall speed.
The usual approach to a high speed divider is to cascade divide-by-two sections, each consisting of two D latches connected as a master-slave flip-flop with inverted feedback from the output to the input. Usually, a simple latch circuit is used which slews through a full logic swing on each state transition. A technique to bias such circuits in the direction of the next state transition is described in U.S. Pat. No. 5,324,997, but it does not work as well as a novel high-speed divider circuit presently disclosed.
In the following description, like reference numbers are used to identify like elements. Furthermore, the drawings are intended to illustrate major features of exemplary embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of every implementation.